CNSA 2.0 complia t IP co e fo FPGAs a d ASICs p ovides full ha dwa e offload of ML-KEM a d ML-DSA
Gai esville, FL, Nov. 02, 2026 (GLOBE NEWSWIRE) — StealthCo es today a ou ced the lau ch of StealthPQ, a post-qua tum c yptog aphy IP co e fo FPGAs a d ASICs. StealthPQ p ovides full ha dwa e offload of ML-KEM a d ML-DSA, the NIST post-qua tum sta da ds fo key establishme t a d digital sig atu es. It suppo ts all six pa amete sets of FIPS 203 a d FIPS 204. These i clude ML-KEM-1024 a d ML-DSA-87, the pa amete sets equi ed fo CNSA 2.0 complia ce. The optio al cou te measu e co figu atio adds p otectio agai st side-cha el, fault a d glitch attacks.
Post-qua tum algo ithms p otect agai st the th eat of qua tum compute s, but they do ot p otect the ha dwa e that u s them. Side-cha el attacks ecove sec et keys f om the powe co sumptio o elect omag etic emissio s of a device. Glitch attacks distu b a device du i g a ope atio to fo ce e o s that expose keys o bypass secu ity checks. Resea che s have demo st ated both types of attack agai st impleme tatio s of post-qua tum algo ithms. These attacks ta get the impleme tatio , so the defe se must be built i to the impleme tatio .
StealthCo es desig ed the StealthPQ cou te measu e co figu atio to p ovide this p otectio . It applies c yptog aphic maski g to all sec et-depe de t ope atio s. The cou te measu e co figu atio also i cludes ove 30 specific fault a d glitch attack p otectio s, such as a dual-lockstep co t olle . A detected fault locks the co e u til all keys a e e ased.
“The ew algo ithms solve the qua tum p oblem, but they do ot solve the impleme tatio p oblem. A attacke with physical access ca still go afte the keys th ough side-cha el a d glitch attacks. Defe di g agai st those attacks takes p otectio desig ed i to the ha dwa e, a d that has always bee the focus of StealthCo es. StealthPQ b i gs that expe tise to post-qua tum c yptog aphy.”
Stua t Audley, P eside t of StealthCo es
The Need fo Post-Qua tum C yptog aphy
A la ge-scale qua tum compute would b eak the public-key algo ithms that p otect most systems today. E c ypted data captu ed ow could be dec ypted o ce such a machi e exists. Digital sig atu es could be fo ged. Systems built o FPGAs a d ASICs ofte stay i se vice fo decades, so thei c yptog aphy must be eady befo e they ship. U.S. atio al secu ity systems a e al eady o a fixed schedule. U de NSA guida ce, ew acquisitio s fo those systems a e expected to suppo t CNSA 2.0 f om Ja ua y 2027.
Key Featu es a d Capabilities
StealthPQ pe fo ms each ope atio i full, f om key ge e atio th ough sig i g a d decapsulatio . The host sta ts a ope atio th ough a si gle AXI4-Lite i te face a d eads the esult whe the co e sig als completio . P ivate keys a e ge e ated i secu e i te al key slots a d emai the e. Softwa e efe s to each key by its slot umbe . The sha ed sec et of a key establishme t leaves the co e o a dedicated output. That output co ects di ectly to StealthKey o a othe key sto e.
StealthPQ is NIST ACVTS eady. ACVTS is NIST’s Automated C yptog aphic Validatio Testi g System. A ACVP ha ess with validatio suppo t is available as a optio .
“StealthPQ makes ha dwa e-level post-qua tum c yptog aphy a i teg atio task athe tha a complex c yptog aphic desig a d ve ificatio task,” added Audley.
Pe fo ma ce a d I teg atio
The Fast co figu atio completes up to 12,400 ML-KEM-768 e capsulatio s a d 5,190 ML-DSA-65 ve ificatio s pe seco d at 200 MHz. At the highest secu ity level, it completes up to 9,270 ML-KEM-1024 e capsulatio s a d 3,640 ML-DSA-87 ve ificatio s pe seco d. These figu es apply to the co figu atio s without the cou te measu e optio .
Custome s ca also select a co figu atio with ML-KEM o ML-DSA alo e. StealthPQ is delive ed i Ve ilog o VHDL fo eve y majo FPGA family a d fo ASIC impleme tatio . Softwa e suppo t i cludes the StealthAPI lib a y, a Li ux d ive a d wolfSSL i teg atio .
Full CNSA 2.0 Secu ity Suite
StealthPQ completes the CNSA 2.0 Secu ity Suite f om StealthCo es. The suite p ovides CNSA 2.0 complia t AES-256 with StealthAES, SHA-384 a d SHA-512 with StealthSHA, a d ML-KEM-1024 a d ML-DSA-87 with StealthPQ. The co es sha e commo i te faces a d o e softwa e lib a y.
Two ew co es joi the suite. StealthKey is a ha dwa e key ma age that ge e ates, de ives, w aps a d delive s keys fo the othe co es. It takes the StealthPQ sha ed sec et di ectly i ha dwa e. Softwa e the efo e eve holds the sessio keys. StealthEC is a optio al additio . It p ovides ECDSA sig i g a d ve ificatio a d ECDH key ag eeme t o the NIST P-384 a d P-256 cu ves i a compact desig . It suppo ts CNSA 1.0 systems du i g the t a sitio . It also supplies the classical half of a hyb id key excha ge alo gside ML-KEM.
Ta get Applicatio s
StealthPQ ta gets key establishme t fo TLS 1.3, IPsec IKEv2 a d MACsec. It also se ves fi mwa e a d code sig i g, secu e boot ve ificatio , sig i g se ve s a d ha dwa e secu ity modules, a d device ide tity a d p ovisio i g.
The Sta da d a d Fast co figu atio s of StealthPQ a e available ow fo FPGA a d ASIC impleme tatio s. Fo detailed specificatio s, pe fo ma ce data a d i teg atio suppo t, co tact the StealthCo es team at i fo@stealthco es.com.
About StealthCo es
StealthCo es develops adva ced secu ity IP fo FPGAs a d ASICs, delive i g p actical, high-pe fo ma ce c yptog aphic solutio s with built-i cou te measu es agai st side-cha el attacks. Backed by decades of i dust y expe ie ce a d pu pose-built IP, StealthCo es e ables custome s to secu e c itical systems with co fide ce. Lea mo e at www.stealthco es.com o co tact us at i fo@stealthco es.com.
Media Co tact
StealthCo esi fo@stealthco es.com(352) 297-2244
