CAMBRIDGE, United Kingdom and MUNICH, June 09, 2026 (GLOBE NEWSWIRE) — lowRISC C.I.C., the open-silicon ecosystem organization, and the Fraunhofer Institute for Applied and Integrated Security AISEC, one of Europe’s leading institutions for cybersecurity research, today announced that Fraunhofer has officially joined the OpenTitan® project as a key security testing partner. By bringing its world-renowned hardware evaluation expertise to the world’s first open-source silicon Root of Trust (RoT), Fraunhofer will play a critical role in independently validating the project’s resilience against advanced physical and logical attacks.
OpenTitan, stewarded by the not-for-profit lowRISC®, relies on a transparent, community-driven methodology to build commercial-grade secure silicon designs. While open-source transparency allows for widespread code inspection, true hardware security also demands rigorous, specialized physical testing. Fraunhofer AISEC’s Common Criteria (CC)-certified Hardware Security Lab will provide exactly that, offering cutting-edge evaluations including side-channel analysis, fault injection testing, and secure boot verification.
“Radical transparency in silicon design only achieves its full potential when paired with ruthless, independent testing,” said Javier Orensanz Martinez, CEO of lowRISC. “Fraunhofer AISEC is globally respected for its deep expertise in applied hardware security and physical attack mitigation. Having them join the OpenTitan coalition as a dedicated testing partner ensures that the OpenTitan open-source Root of Trust can confidently withstand the most sophisticated attacks in the wild.”
As a security testing partner, Fraunhofer will collaborate with the OpenTitan coalition to evaluate the physical resilience of the project’s silicon designs, such as the Earl Grey top level. By analyzing and testing the hardware architecture before and after tape-out, Fraunhofer will help the community refine its countermeasures, harden its cryptographic accelerators (including early integration of post-quantum cryptography), and ensure the design meets the highest evaluation assurance levels.
Evaluation of the security properties
In cooperation with the design teams from Google, lowRISC and Nuvoton Fraunhofer AISEC has evaluated the hardware security of OpenTitan engineering and production silicon. The goal was to analyze OpenTitan’s security under a strong attack model before deployment in servers and Chromebooks. The evaluation analysed OpenTitan’s core security properties and led to several hardening measures and tooling improvements that benefit future tape-outs and deployments of the OpenTitan silicon root-of-trust.
“We strongly believe that open-source hardware is a vital component for the future of technological sovereignty and trusted electronics,” stated Prof. Dr. Georg Sigl, Institute Director at Fraunhofer AISEC. “OpenTitan represents a paradigm shift in how secure silicon is developed. We are thrilled to apply our comprehensive spectrum of offensive hardware security analyses to this project, ensuring that the open-source community’s innovations are matched by uncompromising physical robustness. With the additional high-end lab‑equipment investment made possible by initiatives like APECS and Trusted Electronic Bavaria Center (TrEB), which support applied research in trusted electronics, we can broaden our security‑analysis portfolio and extend it to cover emerging System-on-chips and chiplet technologies.”
Fraunhofer joins a rapidly growing and distinguished OpenTitan coalition.
For more information about the OpenTitan project, its commercial availability, and how to get involved, please visit opentitan.org.
About Fraunhofer AISEC
The Fraunhofer Institute for Applied and Integrated Security AISEC is considered one of the world-leading institution for applied research in cybersecurity. Around 230 highly qualified researchers develop customized security concepts and solutions for commercial businesses and the public sector, boosting the overall competitiveness of clients and partners. Fraunhofer AISEC designs solutions for enhanced data security and effective defense against cybercrimes such as corporate espionage and tampering attacks. The institute’s portfolio ranges from embedded and hardware security, automotive and mobile security to security solutions for industry and automation. In addition, the cutting-edge test labs at Fraunhofer AISEC allow for evaluating the security of networked and embedded systems, hardware and software products as well as cloud and web-based services.
https://www.aisec.fraunhofer.de/en.html
APECS (Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems) is a European pilot line established under the EU Chips Act. By providing large industry players, SMEs, and start-ups with easier access to cutting-edge technology, the APECS pilot line will build a strong foundation for resilient and robust European semiconductor supply chains.
The Trusted Electronic Bavaria Center (TrEB) (in German) researches technologies for trustworthy electronics and tests them in prototype implementations in order to support industrial customers and public partners in securing the electronics in their products and systems with practically applicable solutions.
About lowRISC
Founded in 2014 at the University of Cambridge, lowRISC C.I.C. is a not-for-profit company that provides a neutral home for collaborative engineering to develop and maintain open-source silicon designs and tools for the long term. The lowRISC open-source silicon ecosystem includes the OpenTitan project, which aims to make open-source silicon work the same way as open-source software. Find more information at http://www.lowrisc.org.
Media Contacts:
lowRISC C.I.C.
Media Relations
Email: lowrisc@w2comm.com
Website: http://www.lowrisc.org
Fraunhofer AISEC
Corporate Communications
Email: prm@aisec.fraunhofer.de
Website: http://www.aisec.fraunhofer.de
