GAINESVILLE, Fla., March 19, 2026 (GLOBE NEWSWIRE) — The 2026 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded earlier this month with record attendance at its new Santa Clara, California venue. The conference celebrated innovation across the design and verification community, announcing the 2026 Stuart Sutherland Best Paper and Best Poster winners during the March 4 evening reception, along with the first-ever DVCon U.S. Hackathon winners.
Participants from 29 countries, representing approximately 350 companies, attended the conference, including 598 first-time attendees. The event featured 34 sponsors and exhibitors, 5 for the first time. Overall attendance, including representatives from exhibiting companies, reached 1,243, a 17% increase from last year. The exhibits were also at capacity.
“I am thrilled with the success of DVCon U.S. 2026,” said Xiaolin Chen, DVCon U.S. 2026 General Chair. “Technical sessions were exceptionally well attended, and the exhibition floor was vibrant with discussion as attendees connected with colleagues and explored the latest innovations in design and verification. Our keynotes and panel discussion offered valuable perspectives on the growing role of artificial intelligence in the verification ecosystem. With our new Santa Clara venue providing additional space to grow, DVCon continues to expand as the industry’s premier forum for sharing ideas, advancing methodologies, and strengthening the design and verification community.”
The first-place award for the Stuart Sutherland Best Paper Presentation, as voted by conference attendees, was presented to Matthew Ballance of AMD for the paper, “Properly Introducing Python to Your UVM Testbench.” The second-place award went to Jamie Ridgeway of Paradigm Works for “Visualizing SystemVerilog and UVM.” Third place was awarded to Yunsheng Bai, Ghaith Bany Hamad, Chia-Tung (Mark) Ho, Syed Suhaib, and Haoxing (Mark) Ren of NVIDIA for their paper, “FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures.”
Top honors for the Best Poster was presented to Bryan Morris and Michael Silveira of Ciena Corp for their poster, “plusargs++: Make Plusargs Great … Like They Never Were Before.” Second place was awarded to Tom Fitzpatrick of Big Fish EDA for “There and Back Again: Simulation-to-Synthesis Scenario Reuse with PSS.” Third place went to Bhaskar Vedula, Ganesh Sharma, Stephen Haake, and Chandrakanth Betageri of Intel Corporation for their poster, “Taming Configuration Complexity: A UVM-Based Approach to IP Verification.”
Highlights of the Week:
- The industry keynote on Tuesday, “Beyond Bigger Designs: Rethinking Verification for the Era of Convergence,” was presented by Abhi Kolpekwar, Senior Vice President, Digital Verification Technology, Siemens EDA; Jean-Marie Brunet, Senior Vice President, Hardware Assisted Verification, Siemens EDA; and Alon Shtepel, Senior Director, ASIC Verification and Emulation, Micron Technology. The speakers examined how AI-driven, software-defined, and increasingly modular semiconductor systems are transforming verification challenges, shifting the focus from design size to complex interactions across hardware, software, workloads, and execution platforms. The thought-provoking session drew a full audience of conference attendees.
- Wednesday morning opened with a lively panel discussion titled “Is AI the Key to Ending the Verification Bottleneck?” Moderated by Vishal Karna, Senior Director of Engineering at Qualcomm Technologies, the session brought together industry leaders from AI, EDA, and semiconductor design to examine the role artificial intelligence could play in addressing one of the industry’s most persistent challenges. Panelists shared perspectives on both the promise and practical realities of applying AI to verification workflows, engaging the audience in a spirited discussion that concluded with broad agreement that AI will play a significant role in helping relieve the verification bottleneck.
- Wednesday afternoon featured an invited keynote by Stuart Oberman, Vice President of GPU Hardware Engineering at NVIDIA, titled “From Pixels to Tokens: Chip Design and Verification in the Era of AI.” Speaking to a full audience, Oberman emphasized that AI is becoming essential to managing the rapidly growing complexity and pace of GPU and SoC development. Drawing on more than two decades of GPU innovation, he highlighted how AI-driven and agentic workflows are emerging as key tools for scaling design and verification in the next generation of semiconductor systems.
- DVCon U.S. 2026 also hosted its first-ever online Hackathon challenge, sponsored by QuickSilicon, inviting attendees to test their skills on real-world design and verification problems. Attendees could log in on the first day of the conference, competing to achieve the highest accuracy in the shortest time over three days. Rafid Ahmed Jukaku earned first place with a perfect score in just 1 hour and 21 minutes, followed by Felix Dube in second place, and Zili Fang in third place.
Save the date: DVCon U.S. 2027 will be held March 1-4 at the Hyatt Regency in Santa Clara, California. Xiaolin Chen will continue as General Chair for DVCon U.S. 2027.
The proceedings from DVCon U.S. 2026 will be available to the public in June. To view proceedings from past conferences, visit the archives site.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP), and electronic design automation (EDA) companies. For more information about Accellera, please visit http://www.accellera.org. For more information about DVCon U.S., visit the DVCon U.S. website. Follow DVCon U.S. on Facebook, LinkedIn or X.
