SAN JOSE, Calif., Feb. 20, 2025 (GLOBE NEWSWIRE) — Breker Verification Systems today confirmed its RISC-V SystemVIP library components and test suite synthesis product portfolio is deployed in more than 15 commercial RISC-V semiconductor design projects, while its RISC-V products are used in several large-scale academic projects.
Large, complex application processor projects that range from data center, automotive and AI accelerator to consumer device applications rely on Breker’s RISC-V CoreAssurance™, SoCReady™ and Cache Coherency SystemVIPs across the RISC-V core and SoC verification stack. Breker executives are heading working groups in the evolving RISC-V International certification program.
“Breker Verification Systems’ products provide significant advantages on top of standard verification solutions, especially for the most challenging verification problems,” affirms Ty Garibay, President of Condor Computing. “Applying these approaches to RISC-V processor design was a natural extension, and leveraging this technology in the development of our high-performance CPU IP is already paying dividends.”
Breker’s test suite synthesis solution and SystemVIP library allow for enhanced verification coverage while significantly reducing test development time for complex scenarios. The verification of processor cores that leverage the RISC-V Open Instruction Set Architecture (ISA) requires testing specialized, unique scenarios. Breker’s RISC-V synthesized SystemVIPs make use of AI Planning Algorithms, cross-test multiplication and concurrent, multi-threaded scheduling provide rigorous testing from randomized instructions to unique coherency, paging and other complex system integration validation.
“MIPS RISC-V cores represent the state-of-the-art in advanced application processor solutions,” notes Steve Mullinnix, Senior Director, Design Verification, MIPS. “Working with Breker, we are able to verify complex, compounded scenarios unique to these devices quickly and efficiently.”
Breker is cooperating with academic institutions including Harvey Mudd College in Claremont, Calif., and Oklahoma University, developers of the Wally open-source processor core, and ETH Zurich in Zurich, Switzerland, that produced the Ariane processor core. Breker has provided application-level tests for these institutions while collaborating on next-generation verification environments.
“Breker is at the forefront of RISC-V verification,” comments David Harris, the Harvey S. Mudd Professor of Engineering Design. “It’s first-rate SystemVIP synthesis platform is a breakthrough verification tool and an effective problem-solver for our RISC-V programs.”
Additionally, executives from Breker are leading two working groups within RISC-V International’s Certification Steering Committee to develop a program to provide a quality stamp based on extensive, independent architectural testing.
“The rate of adoption of our tools is remarkable and supports our belief that test suite synthesis is a must have tool for every RISC-V design project,” says David Kelf, Breker’s Chief Executive Officer. “Our efforts to build more features will continue as will our willingness to partner with leading project groups and industry organizations helping to cement the RISC-V ISA place across the semiconductor industry.”
Breker’s RISC-V CoreAssurance, SoCReady and SystemVIP
Breker unveiled RISC-V CoreAssurance, SoCReady and SystemVIP in June 2024, along with a complete range of tests for the entire RISC-V core verification stack. Starting with randomized instruction generation and microarchitectural scenarios, SystemVIP includes unique tests that check all integrity levels ensuring the smooth application of the core into an SoC, regardless of architecture, and the evaluation of possible performance and power bottlenecks and functional issues.
The SystemVIP can be extended for custom RISC-V instructions to be fully incorporated into the complete test suite crossed with other tests. It is self-checking and incorporates debug and coverage analysis solutions and can be ported across simulation, emulation, prototyping, post-silicon and virtual platform environments.
Breker’s SystemVIP is used for a variety of complex RISC-V core designs, including system coherency in a multicore SoC integrity test sets, high-coverage core test, power domain switching, hardware security access rules and automated packet generation
Breker at DVCon U.S. February 24-27 in San Jose
Breker will exhibit and demonstrate its RISC-V CoreAssurance and SoCReady SystemVIP and Trek Test Suite Synthesis solutions at DVCon U.S. February 24-26 at the DoubleTree Hotel in San Jose, Calif.
It will present a workshop titled “Complex Verification Example: RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC platforms” Monday, February 24, from 3:30 p.m. until 5 p.m. in the Oak Room.
To arrange a demonstration or private meeting, send email to info@brekersystems.com.
About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker solutions easily layer into existing environments and operate across simulation, emulation and prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Altera (now Intel), Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.
Engage with Breker at:
Website: http://www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
Facebook: https://www.facebook.com/BrekerSystems/
TrekSoC, TrekSoC-Si, TrekBox and SoC Scenario Modeling are registered trademark of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.
For more information, contact:
Nanette Collins
Public Relations for Breker Verification Systems
nanette@nvc.com
