Verific App Store Opens with Downloadable Examples of Parser Platform Applications

• I itial offe i gs i clude a hie a chy explo e , li te , HDL edito , sig al t ace , esse tial tools fo ha dwa e desig a d ve ificatio
• Ve ific App Sto e ope s July 27 as 63 d DAC begi s i Lo g Beach, Calif.

ALAMEDA, Calif. , July 22, 2026 (GLOBE NEWSWIRE) — Ve ific Desig Automatio today a ou ced the Ve ific App Sto e with a toolkit a d dow loadable example applicatio s showcasi g a va iety of esse tial elect o ic desig automatio (EDA) poi t tools a d solutio s built usi g its Pa se Platfo ms.

The Ve fic App Sto e will ope Mo day, July 27, as the 63 d Desig Automatio Co fe e ce (DAC) co ve es at the Lo g Beach Co ve tio Ce te i Lo g Beach, Calif. Ve ific will offe i DAC Booth #1052 demo st atio s of the ew Ve ific App Sto e examples alo g with demo st atio s of its SystemVe ilog, Ve ilog, VHDL a d UPF f o t-e d Pa se Platfo ms.

“We wa t to show how you ca build eally cool EDA p oducts with ou Platfo m,”  ema ks Rob Dekke , Ve ific’s p eside t, fou de a d CTO. “I the Ve ific App Sto e, we sta ted with a umbe of useful EDA poi t tools that a e fast u i g, simple to lice se a d easy to use by AI a d HI (Huma I tellige ce) alike.”

As the leadi g p ovide of f o t-e d platfo ms, Ve ific powe s EDA with its SystemVe ilog, Ve ilog, VHDL a d UPF pa se softwa e used as the fou datio fo both i -house a d comme cially available EDA tools a d flows. Applicatio s a ge f om sy thesis a d fo mal ve ificatio to emulatio , debuggi g, vi tual p ototypi g, low-powe desig a d desig -fo -test tools.

Cu e tly Available Pa se Platfo m AppsExample apps cu e tly available at the Ve ific App Sto e i clude a hie a chy explo e , a li te , a HDL edito a d a sig al t ace , esse tial tools fo ha dwa e desig a d ve ificatio .

Hie RTL is a Hie a chy Explo e that epo ts the st uctu al hie a chy of Ve ilog, SystemVe ilog, a d VHDL desig s di ectly f om the pa se t ee without the eed fo elabo atio . E gi ee s ca visualize a d avigate the hie a chical st uctu e of thei desig s a d u de sta d elatio ships betwee diffe e t modules a d compo e ts, maki g it easie to ma age complex desig s.

Li tRTL is a Li te tool fo SystemVe ilog a d VHDL that ide tifies desig issues ea ly with co figu able li t ules a d adva ced sy thesizability checks. It a alyzes code fo pote tial e o s, style issues a d adhe e ce to codi g sta da ds. It helps e su e that the HDL code is clea a d mai tai able, educi g bugs befo e simulatio o sy thesis.

S apRTL is a automated HDL edito used to a alyze, modify a d expo t desig s while p ese vi g the o igi al code a d fo matti g. It gives e gi ee s co fide ce to be able to modify thei desig s i a specialized e vi o me t fo w iti g a d editi g HDL code. S apRTL featu es sy tax highlighti g, code completio a d e o detectio , st eamli i g the codi g p ocess a d imp ovi g p oductivity.

T aceRTL is a Sig al T ace fo SystemVe ilog a d VHDL to imp ove t aceability a d speed debug. It mo ito s a d a alyzes sig als withi the desig a d p ovides i sights i to sig al behavio du i g simulatio , helpi g e gi ee s effectively debug a d optimize thei desig s.

Additio al apps will be added i the futu e.

Availability a d P ici g“We will be addi g mo e EDA poi t tools as we go,” says Dekke . “Cu e tly most base p oducts a e f ee of cha ge, a d we o ly cha ge a small fee fo mo e adva ced p oduct featu es.”

The Ve ific App Sto e will ope July 27. Tool flow develope s ca dow load the tools i the Ve ific Toolkit with o without bei g a existi g Ve ific custome , but egist atio is equi ed. New use s will be asked to egiste with a Ve ific Passpo t accou t.

Basic tools a e cu e tly f ee, but adva ced featu es equi e a mo thly subsc iptio fee. F ee evaluatio s a e available fo 14 days.

The Ve ific App Sto e ca be fou d at:  https://sto e.ve ific.com/

Ve ific at DACAtte dees ca a a ge demos o p ivate meeti gs with Ve ific du i g DAC exhibit hou s July 27-29 by se di g email to i fo@ve ific.com.

DAC egist atio is ope .

About Ve ific Desig Automatio Ve ific Desig Automatio is the leadi g p ovide of SystemVe ilog, Ve ilog, VHDL a d UPF Pa se Platfo ms that e able p oject g oups wo ldwide to develop adva ced elect o ic desig automatio (EDA) p oducts quickly a d cost effectively. Ve ific’s softwa e se ves as the f o t e d to sy thesis, fo mal ve ificatio , emulatio , debuggi g, vi tual p ototypi g, low-powe desig a d desig -fo -test tools. With offices i Alameda, Calif., a d Kolkata, I dia, Ve ific has shipped mo e tha 80,000 copies of its softwa e used by the EDA a d semico ducto i dust y si ce it was fou ded i 1999.

E gage with Ve ific at:Email: i fo@ve ific.comWebsite: www.ve ific.comLi kedI : https://www.li kedi .com/compa y/ve ific-desig -automatio -i c/

Fo mo e i fo matio , co tact:Na ette Colli sPublic Relatio s fo Ve ific a ette@ vc.com